- Pezy insists workloads demand more independence than lockstep mainstream execution allows
- Pezy SC4s simulations claim massive efficiency improvements over previous generation designs
- Chip fabricated on TSMC 5nm with unusually large die size
At Hot Chips 2025, a small Japanese firm known for unconventional hardware, presented its latest project, the Pezy SC4s.
Unlike mainstream chipmakers that have standardized around Single Instruction Multiple Data designs, Pezy Computing continues to pursue Multiple Instructions Multiple Data (MIMD).
MIMD can be likened to a society of states, prefectures, cities, and villages, where each unit acts with a degree of independence rather than following a single central authority.
Architecture and fabrication choices
MIMD is not a new idea – after all, every modern laptop for programming runs multiple tasks at once, but it has rarely been implemented on a truly massive scale involving hundreds or thousands of cores.
The design philosophy assumes that future workloads will not always benefit from lockstep execution and that more independent thread handling could become essential.
This makes its strategy distinct from the direction of most so-called best CPU contenders which dominate the global market.
SC4s is manufactured on TSMC’s 5nm process and is not a small chip in terms of physical footprint.
With a die size of around 556mm2, it is considerably larger than many consumer or workstation processors.
However, the emphasis is not on minimizing silicon area but rather on testing whether the benefits of massive parallelism outweigh the costs.
The idea of CPUs having hundreds of cores has been around for a while. Pezy argues that many small, semi-autonomous cores may succeed where centralized approaches struggle.
In effect, the company is betting that computational demand in certain specialized domains justifies this scale, even although such an approach may be impractical for broader consumer adoption.
But what Pezy Computing released is performance simulations rather than final silicon benchmarks, which naturally raises questions about how well these claims will hold in practice.
In comparison to its earlier SC3 design, the SC4s is projected to deliver more than twice the power efficiency when handling a DGEMM workload.
Meanwhile, simulations of the Smith-Waterman algorithm, used in genome sequence alignment, suggest nearly a fourfold increase in performance.
While these figures are impressive on paper, skepticism remains until independent testing validates them.
Historically, bold projections in semiconductor development have not always aligned with measured results once real hardware ships.
Despite the SC4s still being under development, the company has already moved its attention to a successor.
Work is ongoing on a fifth-generation processor, tentatively referred to as Pezy 5, which is expected to use a 3nm or smaller process.
A release window has been set for 2027, although such long-term schedules in chip development often shift due to technical or economic challenges.
Given the scale of the undertaking, industry observers remain cautious about whether the timeline is realistic.
Via Serve The Home
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